Semiconductor memory device and method of controlling auto-refresh

ABSTRACT

Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and amethod of controlling auto-refresh of the semiconductor device. Morespecifically, the present invention relates to a semiconductor memorydevice that refreshes a memory cell corresponding to an addressgenerated by an internal address counter upon input of a predeterminedcommand.

Priority is claimed on Japanese Patent Application No. 2009-011381,filed Jan. 21, 2009, the content of which is incorporated herein byreference.

2. Description of the Related Art

A dynamic random access memory (DRAM) is a semiconductor memory devicehaving a unit memory cell of a selection transistor and a data storagecapacitor, selecting a specific memory cell out of plural memory cellsby the use of a row/column address, and reading and writing data fromand to the selected memory cell. However, the capacitor as a storagenode is volatile and it is thus necessary to rewrite (refresh) data at apredetermined interval. In the specifications thereof, the number ofrefresh operations and the maximum refresh interval are determined.Japanese Unexamined Patent Application, First Publication, No.JP-A-2008-135113 discloses the followings. The refresh modes areclassified into an auto-refresh (AREF) mode and a self refresh mode. TheAREF is a mode in which a memory cell corresponding to an addressgenerated by an internal address counter is performed in a tRFC period(a period from an AREF command to an ACT/AREF command) when the AREFcommand is input. After the refresh operation, the address counter isupdated and is provided for the next AREF command.

The self refresh is a mode in which a refresh operation is performedevery time at a frequency determined by an internal oscillation circuit(oscillator) while a CKE signal is in the “L” level, when the CKE (ClockEnable) signal is set to the “L” level at the same time as an REFcommand. In the self refresh mode, it is possible to adjust thetrade-off relation between the current consumption and the dataretention time by adjusting the period of the internal oscillator.Control methods of giving temperature dependency to the refresh period,changing the period using a temperature sensor, and the like have beenperformed as a method of reducing the current consumption in the selfrefresh mode. However, in the self refresh mode, since the CKE signal isin the “L” level, an external clock signal is not input to the DRAM.Accordingly, after it exits from the self refresh mode, there is aproblem in that a long period of time is necessary for re-locking asynchronization circuit such as a DLL (Delay Lock Loop) and data cannotbe read just after it exits from the self refresh mode.

On the other hand, in the AREF mode, data can be read just after thetRFC. Accordingly, the AREF mode has been often used when the systemfrequently operates. The AREF mode generally employs an 8K-refresh(8KREF) mode in the recent DRAM specification. The 8K-refresh mode is amode in which an address is returned to an initial address after an AREFcommand is repeated 8192 times. However, when the data retention time isshortened for reasons of variation in the characteristics of asemiconductor device and the like, data may disappear even when it isintended to refresh the initial address after the 8192 times.

SUMMARY

In one embodiment, a semiconductor device may include, but is notlimited to, an auto-refresh command detector that detects anauto-refresh command, and a refresh number setting unit that sets thenumber of auto-refresh to be performed in a period of time, based ontemperature, when the auto-refresh command detector detects theauto-refresh command.

In another embodiment, a device may include, but is not limited to, amemory array including a plurality of sets, each of the plurality ofsets including a plurality of memory elements, and a control circuitperforming a first refresh operation on a first number of sets in theplurality of sets in response to a first refresh command, the number ofthe first number of sets being dependent on a variation in temperatureof the device.

In still another embodiment, a method of controlling auto-refresh of asemiconductor device may include, but is not limited to, setting thenumber of auto-refresh to be performed in a period of time, based ontemperature, every time an auto-refresh command is detected.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a semiconductor memory device inaccordance with one embodiment of the present invention;

FIG. 2 is a circuit diagram illustrating the configuration of atemperature detecting circuit included in the semiconductor memorydevice of FIG. 1;

FIG. 3 is a diagram illustrating temperature-voltage characteristic ofthe temperature detecting circuit of FIG. 2;

FIG. 4 is a diagram illustrating temperature-output characteristic ofthe temperature detecting circuit of FIG. 2;

FIG. 5 is a circuit diagram illustrating the configuration of a refreshnumber setting circuit included in the semiconductor memory device ofFIG. 1;

FIG. 6 is a truth table showing input-output characteristic of therefresh number setting circuit of FIG. 5;

FIG. 7 is a circuit diagram illustrating the configuration of a countercircuit included in the semiconductor memory device of FIG. 1;

FIG. 8 is a circuit diagram illustrating the configuration of a refreshstart signal generating circuit included in the semiconductor memorydevice of FIG. 1;

FIG. 9 is a timing chart illustrating operations of the semiconductormemory device of FIG. 1;

FIG. 10 is a block diagram illustrating a semiconductor memory device inaccordance with another embodiment of the present invention;

FIG. 11 is a block diagram illustrating a semiconductor memory deviceincluding an oscillator which controls self-refresh operations; and

FIG. 12 is a circuit diagram illustrating the configuration of a refreshnumber setting circuit included in the semiconductor device of FIG. 11.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before describing the present invention, the related art will beexplained in detail, in order to facilitate the understanding of thepresent invention.

Data retention time depends on temperature. In general, data retentiontime is likely to become shorter as temperature increases. Shorter dataretention time needs more frequent refresh operations. It is difficultto shorten the time interval between AREF commands on an externalsystem. Thus, 5.3K-refresh method (5.3KREF method) and 4K-refresh method(4KREF) can be adopted to avoid data loss. 5.3K-refresh method is torefresh 1.5 times in the period of time tRFC. 4K-refresh method is torefresh 2 times in the period of time tRFC. Increase in the number ofrefresh operations in the period of time tRFC will increase theoperating current IDD5 (AREF current). If the frequent refresh methodsuch as the 5.3K-refresh method and the 4K-refresh method is onceadopted, it is difficult to reduce the current. Generally, advancedsystems need to reduce the consumption of power as much as possible.DRAMs also need to reduce the consumption of power as much as possible.Under these requirements, it is difficult to adopt the 5.3K-refreshmethod (5.3KREF method) or the 4K-refresh method (4KREF).

The refresh timings are not adjustable or controllable depending upontemperature as long as the refresh is performed in accordance with theauto-refresh command (AREF) as the external command. The auto-refreshcommand (AREF) is given by an external controller which is outside theDRAM chip. This method is different from self-refresh methods usingrefresh commands generated inside the DRAM chip. The auto-refresh methodis adopted for each DRAM chip by previously setting the 5.3K-refreshmethod (5.3KREF method) or the 4K-refresh method (4KREF). In somecircumstances in use, the refresh timings are so long as to allow dataloss. In some circumstances in use, the refresh timings are so short asto increase the consumption of current.

The invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teaching ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purpose.

In one embodiment, a semiconductor device may include, but is notlimited to, an auto-refresh command detector that detects anauto-refresh command, and a refresh number setting unit that sets thenumber of auto-refresh to be performed in a period of time, based ontemperature, when the auto-refresh command detector detects theauto-refresh command.

The semiconductor device may further include, but is not limited to, atemperature detector that detects a temperature of the semiconductordevice. The refresh number setting unit sets the number of refresh basedon the temperature detected by the temperature detector.

The semiconductor device may further include, but is not limited to, acommand decoder that decodes an external command. The command decoderoutputs a refresh execution signal if the decoded command is to selectauto-refresh. The semiconductor device may further include, but is notlimited to, a refresh start signal generator that outputs apredetermined number of refresh start signal based on the refreshexecution signal and the detected temperature.

The semiconductor device may further include, but is not limited to, aplurality of memory banks, a temperature detector that detects atemperature of the semiconductor device, and a bank address counter thatcounts a bank address up to an upper limit based on the refreshexecution signal. The upper limit is determined based on the detectedtemperature. The bank address specifies a memory bank in the pluralityof memory banks. The bank address counter carries a counting number at adivision number. The division number is the number of time-division bywhich refresh is performed to the plurality of memory banks.

The semiconductor device may further include, but is not limited to, anaddress counter that counts up an address when carrying the countingnumber. The address selects a word line of the plurality of memorybanks.

The temperature detector detects the temperature by using a plurality ofpower units having different temperature characteristics.

The refresh number setting unit supplies a signal to the refresh startsignal generator. The signal designates the number of outputs of therefresh start signal. The refresh number setting unit supplies thesignal, based on the temperature detected by the temperature detector,every time of inputting the refresh execution signal. The refresh numbersetting unit supplies the signal while retaining the signal.

The semiconductor device may further include, but is not limited to, arefresh controller that controls refresh operations of a selected memorybank of the plurality of memory banks. The selected memory bank isselected by the back address supplied from the bank address counter. Therefresh controller controls the refresh operations in response to aninput of the refresh start signal. The semiconductor device may furtherinclude, but is not limited to, an address selector that selects anaddress supplied from the address counter, in response to the input ofthe refresh start signal. The address selector supplies the address tothe plurality of bank addresses.

In another embodiment, a device may include, but is not limited to, amemory array including a plurality of sets, each of the plurality ofsets including a plurality of memory elements; and a control circuitperforming a first refresh operation on a first number of sets in theplurality of sets in response to a first refresh command. The number ofthe first number of sets is dependent on a variation in temperature ofthe device.

In some cases, the device may further include, but is not limited to, atemperature detector circuit detecting the temperature of the device andsupplying a result of the detecting to the control circuit.

In some cases, the control circuit may include, but is not limited to, adecoder portion; a signal generating portion; and a control portion. Thedecoder portion receives the first refresh command and supplies arefresh execution signal to the generating portion in response to thereceiving of the first refresh command. The signal generating portionreceives the result of the detecting from the temperature detector andthe refresh execution signal from the decoder portion. The signalgenerating portion supplies a refresh start signal to the controlportion such that the control portion performs the first refreshoperation on the first number of sets comprising the sets of memoryelements.

In some cases, the first refresh command may be supplied externally tothe device.

In some cases, the control circuit may generate a plurality of internalrefresh commands in response to a second refresh command at a firstcycle time therein and performs a plurality of second refresh operationsin response to the internal refresh commands. The control circuit mayperform each of the second refresh operations on an associated secondnumber of sets in the plurality of sets memory elements.

In some cases, the number of the associated second number of sets may befree from the variation in temperature of the device.

In some cases, the device may further include, but is not limited to, atemperature detector circuit detecting the temperature of the device andsupplying a result of the detecting to the control circuit. The controlcircuit, when the control circuit receives the first refresh command,may adjust the number of the first number of sets based on the result ofdetecting, and the control circuit, when the control circuit receivesthe second refresh command, may adjust the first cycle time based on theresult of detecting without adjusting the number of the associatedsecond number of sets.

In some cases, the first refresh command may be an auto-refresh commandand the second refresh command is a self refresh command.

In some cases, the number of sets including the part of the sets of thememory elements may increase in response to rising of the temperature ofthe device and may decrease in response to declining of the temperature.

In some cases, the control circuit varies the number of sets includingnonlinearly the part of the sets of the memory elements.

In still another embodiment, a method of controlling auto-refresh of asemiconductor device may include, but is not limited to, setting thenumber of auto-refresh operations to be performed in a period of time,based on temperature, when an auto-refresh command is detected. Themethod may further include, but is not limited to, detecting atemperature of a semiconductor device. The method may further include,but is not limited to, counting a bank address up to an upper limitbased on a refresh execution signal. The upper limit is determined basedon the detected temperature. The bank address specifies a memory bank ina plurality of memory banks. The method may further include, but is notlimited to, carrying a counting number at a division number, thedivision number being the number of time-division by which refresh isperformed to the plurality of memory banks. The method may furtherinclude, but is not limited to, counting up an address when carrying thecounting number, the address selecting a word line of the plurality ofmemory banks.

Hereinafter, embodiments of the invention will be described withreference to the accompanying drawings. FIG. 1 is a block diagramschematically illustrating the configuration of a semiconductor memorydevice 1 constituting a monolithic DRAM. The semiconductor memory device1 shown in FIG. 1 includes memory elements divided into plural memorybanks in a part of a semiconductor device and serves to select one of anauto-refresh mode and a self refresh mode and to refresh the memoryelements. Here, whenever a command for selecting the auto-refresh modeis detected, the number of refresh operations to be performed isselected depending on the temperature of the semiconductor device. Sincethe invention relates to a refresh process when the auto-refresh mode isselected, only signals relating to the refresh process in theauto-refresh mode and control thereof will be described herein.

As shown in FIG. 1, the semiconductor memory device 1 performing arefresh operation includes a refresh controller 2, an address receiver30, a command receiver/decoder 40, an X address selector/buffer circuit60, a temperature detector circuit 70, a refresh number setting circuit80, and eight memory banks from memory bank 0 (100) to memory bank 7(170). The refresh controller 2 includes a refresh start signalgenerator circuit 10, a counter circuit 20, and a refresh operationcontrol circuit 50. The eight memory banks of memory bank 0 (100) tomemory bank 7 (170) each include an X address latch 101 and an X decodertiming control memory array 102 including a memory array having DRAMmemory cells.

In the above-mentioned configuration, when an address signal ADDRESS isinput, for example, from an external DRAM controller, the addressreceiver 30 stores and outputs the input address ADDRESS insynchronization with a predetermined clock signal.

When a command CMD is input from the external DRAM controller, thecommand receiver/decoder 40 decodes the input command CMD. When thedecoded command CMD is an auto-refresh command, the commandreceiver/decoder 40 generates a refresh signal MCRFT and outputs thegenerate refresh signal to the refresh start signal generator circuit 10and the refresh number setting circuit 80. When the decoded command CMDis an ACT command indicating a word line activating command, the commandreceiver/decoder 40 generates an MACT signal and outputs the generatedMACT signal to the X address selector/buffer circuit 60. The MACT signalis a signal for selecting the address ADDRESS input from the outside viathe address receiver 30 as an X address (that is, a row address or aword address) for specifying a word line to be activated in the memoryarray in the memory banks 0 (100) to 7 (170) by the use of the X addressselector/buffer circuit 60 when the ACT command is input.

In this embodiment, the refresh signal MCRFT and the MACT signal outputfrom the command receiver/decoder 40 each are a pulse signal (in the “H”level or the “L” level) with a predetermined pulse width.

The refresh start signal generator circuit 10 outputs a refresh startsignal RREFT by a predetermined number of times on the basis of thetemperature detection result of the temperature detector circuit 70 inresponse to the refresh signal MCRFT. The refresh signal MCRFT is inputto the refresh start signal generator circuit 10 from the commandreceiver/decoder 40. An M4KREFT signal, an M53KREFT signal, and anM8KREFT signal output from the refresh number setting circuit 80 areinput to the refresh start signal generator circuit 10. The refreshstart signal generator circuit 10 generates the refresh start signalRREFT at a predetermined interval and by a predetermined number of timeson the basis of the input signals, and outputs the generated refreshstart signal to the counter circuit 20, the refresh operation controlcircuit 50, and the X address selector/buffer circuit 60. Here, theM4KREFT signal, the M53KREFT signal, and the M8KREFT signal are signalsindicating one of three types of refresh modes with different numbers ofrefresh operations (that is, with different refresh periods), and aregenerated by the refresh number setting circuit 80 on the basis of thetemperature detection result of the temperature detector circuit 70.

Only one of the M4KREFT signal, the M53KREFT signal, and the M8KREFTsignal is in the “H” level. In this embodiment, when the M4KREFT signalis in the “H” level, a 4KREF mode (4K-refresh mode) in which the refreshoperation is performed repeatedly 2 times during the tRFC period isselected. When the M53KREFT signal is in the “H” level, a 5.3KREF mode(5.3K-refresh mode) in the refresh operation is performed repeatedly 1.5times during the tRFC period is selected. When the M8KREFT signal is inthe “H” level, a 8KREF mode (8K-refresh mode) in the refresh operationis performed repeatedly 1 time during the tRFC period is selected.Although the details will be described later, in this embodiment, therefresh start signal RREFT is generated from the refresh start signalgenerator circuit 10 by 8 times, 6 times, and 4 times in response to theinput of the refresh signal MCRFT, when the M4KREFT signal, the M53KREFTsignal, and the M8KREFT signal are in the “H” level, respectively.

The counter circuit 20 includes a bank address counter 21 and an Xaddress counter 22. The bank address counter 21 counts up a bank addressBADD which is an address for specifying a memory bank, whenever therefresh start signal RREFT is input. The X address counter 22 counts upan X address XADD for specifying a word line to be activated in responseto the carry output of the bank address counter 21. That is, in thecounter circuit 20, when the highest bit of the bank address BADD of thebank address counter 21 is counted up, that is, when the bank addressBADD is carried, the X address XADD of the X address counter 22 iscounted up. The bank address counter 21 outputs the bank address BADD tothe refresh operation control circuit 50. The X address counter 22outputs the X address XADD to the X address selector/buffer circuit 60.A specific memory bank is selected out of the plural memory banks 0(100) to 7 (170) by the bank address BADD. As described above, therefresh start signal RREFT is generated by the refresh start signalgenerator circuit 10 by the number of times determined depending on thetemperature detected by the temperature detector circuit 70.Accordingly, the bank address counter 21 counts the refresh start signalRREFT whenever the refresh signal MCRFT is generated, up to the numberof times determined depending on the temperature. The bank addresscounter 21 carries the count number at a division number. The divisionnumber is the number of time-division by which the refresh process isperformed to the plurality of memory banks 0 (100) to 7 (170) asdescribed later.

The bank address counter 21 has a division number therein by which therefresh process is performed on the plural memory banks in a timedivisional manner (or at a time interval), and performs the carryprocess at the set division number of the plural memory banks. In thisembodiment, the eight memory banks 0 (100) to 7 (170) are divided intofour set of two memory banks, that is, the division number of memorybanks is set to “4”, and the refresh process is performed on two memorybanks at a time. Accordingly, the bank memory counter 21 repeatedlycounts the bank address BADD of two bits from “0” to “3”. In this case,the bank address “0” is counted after “3” and then the bank address iscounted up again.

The X address counter 22 has a word number of each memory bank as arefresh control target, counts the X address XADD up to the set wordnumber of each memory bank, returns the value of the X address XADD to“0” at the set word number of each memory bank, and then counts up the Xaddress XADD.

The counters of the counter circuit 20, that is, the bank addresscounter 21 and the X address counter 22, retain the count value evenafter the refresh process is once performed. Accordingly, the countercircuit 20 sequentially counts up the retained values of the bankaddress BADD and the X address XADD whenever an auto-refresh command REFis input from the external DRAM controller. As a result, the refreshprocess can be performed on the entire word lines of the memory banks.

When the refresh start signal RREFT is input from the refresh startsignal generator circuit 10, the refresh operation control circuit 50controls the refresh operation on the memory banks (from the memory bank0 (100) to the memory bank 7 (170)) by outputting a refresh controlsignal PMCBATi (where i is an integer of 9 to 7) corresponding to thememory bank selected by the bank address BADD input from the bankaddress counter 21 for a predetermined period of time. That is, therefresh operation control circuit 50 outputs a refresh control signalPMCBAT0 for controlling the refresh operation on the memory bank 0(100), a refresh control signal PMCBAT1 for controlling the refreshoperation on the memory bank 1 (110), . . . , and a refresh controlsignal PMCBAT7 for controlling the refresh operation on the memory bank7 (170). The outputs of the refresh control signals PMCBATi are input tothe corresponding memory banks i.

In this embodiment, as described above, the refresh operation controlcircuit 50 divides the eight memory banks 0 (100) to 7 (170) into foursets each including two memory banks, and performs the refresh processon two memory banks at a time. At this time, the refresh process on thefour sets of memory banks is temporally discretely performed in a timedivisional manner. In a specific combination, the refresh operationcontrol circuit 50 outputs the refresh control signal PMCBAT0 to thememory bank 0 (100) and the refresh control signal PMCBAT7 to the memorybank 7 (170) at the same time. Similarly, the refresh operation controlcircuit 50 outputs the refresh control signal PMCBAT4 to the memory bank4 and the refresh control signal PMCBAT3 to the memory bank 3 at thesame time. Similarly, the refresh operation control circuit 50 outputsthe refresh control signal PMCBAT1 to the memory bank 1 (110) and therefresh control signal PMCBAT6 to the memory bank 6 at the same time.The refresh operation control circuit 50 outputs the refresh controlsignal PMCBAT5 to the memory bank 5 and the refresh control signalPMCBAT2 to the memory bank 2 at the same time.

The method of generating the refresh control signal PMCBATi from therefresh operation control circuit 50 is not limited to theabove-mentioned method. For example, by causing each memory bank togenerate a refresh process end signal, the generation period of time forthe refresh control signal PMCBATi may be controlled on the basis of theend signal.

In response to the input of the refresh start signal RREFT, the Xaddress selector/buffer circuit 60 selects the X address XADD input fromthe X address counter 22 and outputs the selected X address XADD to theX address latches (110 and the like) in the memory banks 0 (100) to 7(170). That is, when the refresh start signal RREFT is input from therefresh start signal generator circuit 10, the X address selector/buffercircuit 60 takes and retains the X address XADD output from the Xaddress counter 22 in response to the input. The refresh start signalRREFT is a signal generated when the command CMD from the external DRAMcontroller is an auto refresh command as described above. When therefresh start signal RREFT is input, the X address selector/buffercircuit 60 selects the retained X address XADD and outputs the selectedX address XADD to the memory banks. When the MACT signal is input fromthe command receiver/decoder 40, the X address selector/buffer circuit60 selects an external address ADDRESS input via the address receiver 30and outputs the selected external address ADDRESS to the memory banks.The MACT signal is a signal generated when the command CMD from theexternal DRAM controller is the ACT command as described above.

In this embodiment, the refresh start signal RREFT and the MACT signalinput to the X address selector/buffer circuit 60 are signals output ina pulse shape for a predetermined period of time. Accordingly, inresponse to the input of the refresh start signal RREFT and the MACTsignal, the X address selector/buffer circuit 60 outputs the X addressXADD or the external address ADDRESS to the memory banks and retains theoutput X address XADD or the output external address ADDRESS until thenext refresh start signal RREFT or the MACT signal is input.

The temperature detector circuit 70 is a circuit detecting thetemperature of the semiconductor device using plural power sourcecircuits having different temperature characteristics and formed in apart of the semiconductor device constituting the semiconductor memorydevice 1. The power source circuit forms a power unit. The temperaturedetector circuit 70 outputs plural signals having different outputlevels for plural different temperatures. In this embodiment, thetemperature detector circuit 70 outputs a signal THTEMPT which is in the“H” level at a temperature equal to or higher than a predeterminedtemperature (temperature A) and a signal TLTEMPT which is in the “H”level at a temperature less than a predetermined temperature(temperature B, where A<temperature<B).

The refresh setting circuit 80 outputs signals indicating the number ofoutput refresh start signals RREFT to the refresh start signal generatorcircuit 10 on the basis of the outputs THTEMPT and TLTEMPT of thetemperature detector circuit 70. The M4KREFT signal, the M53KREFTsignal, and the M8KREFT signal which are the signals indicating thenumber of output refresh start signals RREFT are signals of which theoutput states are retained whenever the refresh signal MCRFT is input.

The memory bank 0 (100) to the memory bank 7 (170) each have a circuitgroup having a function. Here, only the circuit group related to therefresh operation in the memory banks will be described.

The memory bank 0 (100) includes an X address latch circuit 101 for thememory bank 0 and an X decoder timing control memory array 102. The Xdecoder timing control memory array 102 includes an X decoder circuit, atiming control circuit, and a memory cell array.

The X address latch circuit 101 latches and outputs the address outputfrom the X address selector/buffer circuit 60 in response to the inputof the PMCBAT0 signal from the refresh operation control circuit 50. Inresponse to the input of the refresh control signal PMCBAT0 from therefresh operation control circuit 50, the X decoder timing controlmemory array 102 performs the refresh operation on the memory cell inthe word line specified by the address output from the X address latchcircuit 101. The block 1 (110) to the block 7 (170) are circuits for thememory bank 1 to the memory bank 7, respectively, and each has the sameconfiguration and function as the memory bank 0 (100).

The configuration of the temperature detector circuit 70 shown in FIG. 1will be described with reference to FIG. 2. The temperature detectorcircuit 70 shown in FIG. 2 includes a band-gap reference voltage circuit71, a voltage follower circuit 707, and a voltage comparison circuit 72.

The band-gap reference voltage circuit 71 includes an operationalamplifier 701, a resistor 702, a resistor 703, a transistor 704, aresistor 705, and a transistor 706. In this case, the resistor 702 andthe resistor 705 have the same resistance value of R2 and the resistor703 has a resistance value R1 different from R2. The transistor 704 isrepresented by Q1 and the transistor 706 is represented by Q2. Theoutput voltage of the operational amplifier 701 is a reference voltageVBGR not depending on the temperature. The ends of the resistor 702 andthe resistor 705 are connected to the output of the operationalamplifier 701. The other end of the resistor 702 is connected to an endof the resistor 703 and the connection node is connected to thenon-inverting input of the operational amplifier 701. The other end ofthe resistor 703 is connected to the emitter of the transistor 704 whichis a parasitic PNP transistor of the P-type substrate. On the otherhand, the other end of the resistor 705 is connected to the emitter ofthe transistor 706 which is the parasitic PNP transistor of the P-typesubstrate and the connection node is connected to the inverting input ofthe operational amplifier 701.

The voltage follower circuit 707 connects its output to the invertinginput terminal using an operational amplifier and thus outputs the samevoltage VF as the voltage VBGR input to the non-inverting inputterminal.

The voltage comparison circuit 72 includes a resistor 708, a resistor709, a resistor 710, a comparator 711, and a comparator 712. Theresistor 708, the resistor 709, and the resistor 710 are connected inseries in this order and an end of the resistor 708 is connected to theoutput of the voltage follower circuit 707 and the other end thereof isconnected to the resistor 709 and the non-inverting input of thecomparator 711. The other end of the resistor 709 is connected to theresistor 710 and the inverting input of the comparator 712. The otherend of the resistor 710 is connected to the ground (the substratepotential VSS). The inverting input of the comparator 711 and thenon-inverting input of the comparator 712 are connected to theconnection node of the resistor 705 and the transistor 706 in theband-gap reference voltage circuit 71.

In this case, the connection node of the resistor 708 and the resistor709 has a voltage of V1 and the connection node of the resistor 709 andthe resistor 710 has a voltage of V2. The voltage of the connection nodeof the resistor 705 and the emitter of the transistor 706 is representedby VBE(Q2). The output of the comparator 711 is represented by THTEMPTand the output of the comparator 712 is represented by TLTEMPT.

The temperature detector circuit 70 shown in FIG. 2 constitutes asemiconductor temperature sensor detecting a temperature using asemiconductor device formed on the same substrate as the semiconductorsubstrate having the memory device formed thereon. In this example, thesemiconductor temperature sensor uses the fact that the voltage of thePN junction of semiconductor varies depending on the temperature. Morespecifically, in this example, the forward voltage drop VBE (about −2mV/° C.) between the base and the emitter of the transistor is used. Inthis case, the temperature detector circuit 70 forms a circuit detectingthe temperature using two (plural) power source circuits (power units)with different temperature characteristics of the band-gap referencevoltage circuit 71 (first power source unit), which is formed in a partof the semiconductor device), not depending on the temperature and apower source circuit (second power source unit), which includes theresistor 705 and the transistor 706 in the band-gap reference voltagecircuit 71, depending on the temperature.

The output voltage VBGR of the band-gap reference voltage circuit 71makes a characteristic of a positive temperature coefficient using thedifference between currents I1 and I2 flowing in two bipolar transistorsQ1 and Q2 having the same emitter size, and cancels the negativetemperature coefficient of the base-emitter voltage VBE, thereby forminga potential not depending on the temperature. Potentials V1 and V2obtained by dividing the source potential VF hardly depending on thetemperature, which is formed by the voltage follower circuit 707 on thebasis of the VBGR, by resistance are compared with the VBE(Q2) havingthe negative temperature coefficient, thereby detecting the temperature.

That is, VBE(Q2)>V1, V2 is satisfied when the initial temperature is lowas shown in FIG. 3, but the potential of VBE(Q2) is lowered with therising in temperature, V1>VBE(Q2)>V2 is satisfied when the temperatureis higher than the temperature A. When the temperature is higher thanthe temperature B, V1>V2>VBE(Q2) is satisfied. Accordingly, by comparingV1 and V2 with the potential of VBE, it is possible to detect whetherthe temperature is higher than the set temperature. The resistance valueof the voltage VF dividing resistor can be adjusted so that the outputpotential is higher than VBE(Q2) at a desired temperature.

In the voltage comparison circuit 72 shown in FIG. 2, for example, asshown in FIG. 4, the signal THTEMPT is set to the “H” level when thetemperature is equal to or higher than a temperature A and the signalTLTEMPT is set to the “L” level when the temperature is equal to orhigher than a temperature B (A<B). That is, THTEMPT=″L″ and TLTEMPT=“H”are set when the temperature of the semiconductor device is lower thanA, THTEMPT=“H” and TLTEMPT=“H” are set when the temperature of thesemiconductor device is equal to or higher than A and lower than B, andTHTEMPT=“H” and TLTEMPT=″L″ are set when the temperature of thesemiconductor device is equal to or higher than B.

The configuration of the refresh number setting circuit 80 shown in FIG.1 will be described with reference to FIG. 5. The refresh number settingcircuit 80 shown in FIG. 5 outputs the M4KREFT signal, the M53KREFTsignal, and the M8KREFT signal which are the signals indicating thenumber of output refresh start signals RREFT while retaining the outputstate every input of the refresh signal MCRFT on the basis of theoutputs of THTEMPT and TLTEMPT of the temperature detector circuit 70.Here, the block 81 is a circuit block outputting the M4KREFT signal, theM53KREFT signal, and the M8KREFT signal which are the signals indicatingthe number of output refresh start signals RREFT while retaining theoutput state every input of the refresh signal MCRFT. On the other hand,the block 82 is a circuit block setting the M4KREFT signal, the M53KREFTsignal, and the M8KREFT signal regardless of the outputs THTEMPT andTLTEMPT of the temperature detector circuit 70 in a test mode or thelike.

The block 81 includes an AND gate 803 having the output M4KREF of atwo-OR-AND complex gate 801 as a positive logical input and the outputM8KREF of a two-OR-AND complex gate 802 as a negative logical input, anexclusive OR gate 804 (hereinafter, referred to as “EXOR gate 804”)having the output M4KREF and M8KREF as two inputs and having a negativelogical output, and an AND gate 805 having the output M4KREF as anegative logical input and the output M8KREF as a positive logicalinput. The block 81 includes three D flip-flops 806, 807, and 808. Thethree D flip-flops 806, 807, and 808 have the outputs of the AND gate803, the EXOR gate 804, and the AND 805 as their inputs, respectively,and uses the refresh signal MCRFT as a clock signal.

When the refresh signal MCRFT is in the “H” level, the D flip-flop 806receives the output of the AND gate 803, retains the value receivedwhile the refresh signal MCRFT is in the “L” level, and outputs theretained value as the signal M4KREFT. When the refresh signal MCRFT isin the “H” level, the D flip-flop 807 receives the output of the EXORGATE 804, retains the value received while the refresh signal MCRFT isin the “L” level, and outputs the retained value as the signal M53KREFT.When the refresh signal MCRFT is in the “H” level, the D flip-flop 808receives the output of the AND gate 805, retains the value receivedwhile the refresh signal MCRFT is in the “L” level, and outputs theretained value as the signal M8KREFT.

The block 82 includes an inverter 809, a transistor 810, a transistor811, a fuse 812, an inverter 813, an OR gate 814, a transistor 815, atransistor 816, a fuse 817, an inverter 818, an OR gate 819, and a DFT(Design For Test) decoder 820. In this case, a signal PON which is inthe “H” level at the time of turning on the semiconductor memory device1 is input to the inverter 809 and the output of the inverter 809 isconnected to the gates of the transistors 810 and 815. The sources ofthe transistors 810 and 815 are connected to the power source and thedrains thereof are connected to the fuses 812 and 817, respectively. Thedrains of the transistors 810 and 815 are connected to the inputs of theinverters 813 and 818. The drains of the transistors 811 and 816 areconnected to the inputs of the inverters 813 and 818, respectively, andthe outputs thereof are connected to the gates of the transistors 811and 816. The inverter 813 and the transistor 811 constitute a latchcircuit receiving a voltage corresponding to the state of the fuse 812when the signal PON in the “H” level is input, and the inverter 818 andthe transistor 816 constitute another latch circuit receiving a voltagecorresponding to the state of the fuse 817 when the signal PON in the“H” level is input.

The negative logical input of the OR gate 814 is connected to the outputof the inverter 813 and the positive logical input thereof is connectedto one output of the DFT decoder 820. The output of the OR gate 814 isconnected to the OR input of the complex gate 801 and the negativelogical AND input of the complex gate 802. The negative logical input ofthe OR gate 819 is connected to the output of the inverter 818 and thepositive logical input is connected to one output of the DFT decoder820. The output of the OR gate 819 is connected to the OR input of thecomplex gate 802 and the negative logical AND input of the complex gate801.

The external address signal ADDRESS and a signal TMRST for setting theoperation state in the test mode are input to the DFT decoder 820.

In this configuration, the block 82 invalidates the outputs THTEMPT andTLTEMPT of the temperature detector circuit 70 by cutting off the fuse812 and the fuse 815, thereby fixing the operation mode of the refresh.The DFT decoder 820 invalidates the outputs THTEMPT and TLTEMPT of thetemperature detector circuit 70 in the test mode and fixes the refreshoperation mode to a desired state depending on the value of the externaladdress signal ADDRESS.

The block 82 is a circuit invalidating the output of the temperaturedetector circuit 70 and is not directly associated with the features ofthe invention, whereby the block 82 may be omitted. In the followingdescription, it is assumed that the outputs of the OR gate 814 and theOR gate 819 are always in the “L” level, the signal THTEMPT is alwaysequal to the signal M4KREF, and the signal TLTEMPT is always equal tothe signal M8KREF.

In the block 81, the output signals THTEMPT and TLTEMPT (accurately, thesignal M4KREF and the signal M8KREF equal thereto) of the temperaturedetector circuit 70 are decoded by the AND gate 803, the EXOR gate 804,and the AND gate 805. The output of the AND gate 803 is in the “H” levelwhen THTEMPT=″L″ and TLTEMPT=“H”, and the output is in the “L” levelotherwise. The output of the EXOR gate 804 is in the “H” level whenTHTEMPT=“H” and TLTEMPT=“H”, and the output is in the “L” levelotherwise. The output of the AND gate 805 is in the “H” level whenTHTEMPT=“H” and TLTEMPT=″L″ and the output is in the “L” levelotherwise. This is shown in FIG. 6.

FIG. 6 is a truth value table in which the input and output relations ofthe refresh number setting circuit 80 shown in FIG. 5 are arranged. Whenthe temperature of the semiconductor device is lower than apredetermined temperature A, the signal M8KREF is in the “H” level. Whenthe temperature of the semiconductor device is equal to or higher thanthe predetermined temperature A and is lower than a predeterminedtemperature B, the signal M53KREF is in the “H” level. When thetemperature of the semiconductor device is equal to or higher than thetemperature B, the signal M4KREF is in the “H” level. In this way, oneof the signal M8KREF, the signal M53KREF, and the signal M4KREF is inthe “H” level. Therefore, one operation mode can be selected out ofthree operation modes depending on the temperature.

The D flip-flops 806 to 808 are a circuit changing the level of theinput D to be equal to the level of the output Q when a clock input CKis in the “H” level and retaining the level of the output Q when theclock input CK is in the “L” level. The refresh signal MCRFT is input asthe clock input CK to the D flip-flops 806 to 808. The refresh signalMCRFT is a pulse-like signal with a predetermined pulse width being oncein the “H” level when the auto-refresh command is input and theauto-refresh operation is started. Accordingly, whenever the signal inthe “H” level is input as the refresh signal MCRFT, the refresh numbersetting circuit 80 changes the outputs M4KREF, M53KREF, and M8KREF onthe basis of the inputs THTEMPT and TLTEMPT, and retains and outputswhile the refresh signal MCRFT is in the “L” level. Therefore, thetemperature detection result of the temperature detector circuit 70before starting the auto-refresh (AREF) operation is input, therebypreventing the change in operation mode during the AREF period.

The configuration of the counter circuit 20 shown in FIG. 1 will bedescribed with reference to FIG. 7. The counter circuit 20 shown in FIG.7 includes a bank address counter 21 and an X address counter 22. Thebank address counter 21 counts the input refresh start signal RREFT andoutputs 2-bit signals including a signal BA0 and a signal BA1 acquiredas the counting result as the bank address BADD. The X address counter22 counts the signal BA1 and outputs the X address XADD including 13-bitsignals XADD0, XADD1, . . . , XADD12.

The bank address counter 21 includes a D flip-flop 2101, a D flip-flop2102, an inverter 2103, an inverter 2104, a D flip-flop 2105, a Dflip-flop 2106, an inverter 2107, and an inverter 2108. In this case,the output Q of the D flip-flop 2101 is connected to the input D of theD flip-flop 2102, the output Q of the D flip-flop 2102 is connected tothe input of the inverter 2103, and the output of the inverter 2103 isconnected to the input D of the D flip-flop 2101. The refresh startsignal RREFT is input to the clock input CK of the D flip-flop 2101 andthe inverter 2104, and the output of the inverter 2104 is input to theclock input CK of the D flip-flop 2102. The output Q of the D flip-flop2102 is a signal RBA0 of the lowest bit of the X address XADD. Theoutput Q of the D flip-flop 2105 is connected to the input D of the Dflip-flop 2106, the output Q of the D flip-flop 2106 is connected to theinput of the inverter 2107, and the output of the inverter 2107 isconnected to the input D of the D flip-flop 2105. The output of theinverter 2103 is input to the clock input CK of the D flip-flop 2105 andthe inverter 2108, and the output of the inverter 2108 is input to theclock input CK of the D flip-flop 2106. The output Q of the D flip-flop2106 is a signal RBA1 of the second bit from the lowest bit of the Xaddress XADD.

In the above-mentioned configuration, the D flip-flop 2101, the Dflip-flop 2102, the inverter 2103, and the inverter 2104 constitute aone-bit counter circuit changing the level of the signal RBA0 from “H”to “L” or from “L” to “H” whenever the refresh start signal RREFT ischanged from the “H” level to the “L” level. The D flip-flop 2105, the Dflip-flop 2106, the inverter 2107, and the inverter 2108 constitute aone-bit counter circuit changing the level of the signal RBA1 from “H”to “L” or from “L” to “H” whenever the signal RBA0 is changed from the“H” level to the “L” level. Accordingly, the two-bit counter circuit isconstituted by the circuits and the signal RBA0 and the signal RBA1 areoutput as the count result of the two-bit counter. That is, the signalRBA0 and the RBA1 form a two-bit signal counted up to “0”, “1”, “2”,“3”, “0”, “1”, “2”, “3”, . . . whenever the refresh start signal RREFTis changed from the “H” level to the “L” level.

On the other hand, the X address counter 22 includes a D flip-flop 2201,a D flip-flop 2202, an inverter 2203, an inverter 2204, a D flip-flop2205, a D flip-flop 2206, an inverter 2207, an inverter 2208, . . . , aD flip-flop 2209, a D flip-flop 2210, an inverter 2211, and an inverter2212.

In this case, the output Q of the D flip-flop 2201 is connected to theinput D of the D flip-flop 2202, the output Q of the D flip-flop 2202 isconnected to the input of the inverter 2203, and the output of theinverter 2203 is connected to the input D of the D flip-flop 2201. Thesignal obtained by inverting the signal RBA1 by the use of the inverter2107 is input to the clock input CK of the D flip-flop 2201 and theinverter 2204, and the output of the inverter 2204 is input to the clockinput CK of the D flip-flop 2202. The output Q of the D flip-flop 2202is a signal XADD0 of the lowest bit of the X address XADD. The output Qof the D flip-flop 2205 is connected to the input D of the D flip-flop2206, the output Q of the D flip-flop 2206 is connected to the input ofthe inverter 2207, and the output of the inverter 2207 is connected tothe input D of the D flip-flop 2205. The output of the inverter 2203 isinput to the clock input CK of the D flip-flop 2205 and the inverter2208, and the output of the inverter 2208 is input to the clock input CKof the D flip-flop 2206. The output Q of the D flip-flop 2206 is asignal XADD1 of the second bit from the lowest bit of the X addressXADD. The output Q of the D flip-flop 2209 is connected to the input Dof the D flip-flop 2210, the output Q of the D flip-flop 2210 isconnected to the input of the inverter 2211, and the output of theinverter 2211 is connected to the input D of the D flip-flop 2209. Thesignal obtained by inverting the signal XADD11 (not shown) by the use ofthe inverter is input to the clock input CK of the D flip-flop 2209 andthe inverter 2212, and the output of the inverter 2212 is input to theclock input CK of the D flip-flop 2210. The output Q of the D flip-flop2210 is a signal XADD12 of the highest bit (the thirteenth bit from thelowest bit) of the X address XADD. The X address counter 22 includes 13sets of configurations for outputting the signals XADD1 to XADD12 of thebits of the X address XADD.

In the above-mentioned configuration, the D flip-flop 2201, the Dflip-flop 2202, the inverter 2203, and the inverter 2204 constitute aone-bit counter circuit changing the level of the signal XADD0 from “H”to “L” or from “L” to “H” whenever the signal RBA1 is changed from the“L” level to the “H” level. The D flip-flop 2205, the D flip-flop 2206,the inverter 2207, and the inverter 2208 constitute a one-bit countercircuit changing the level of the signal XADD1 from “H” to “L” or from“L” to “H” whenever the signal XADD0 is changed from the “L” level tothe “H” level. The D flip-flop 2209, the D flip-flop 2210, the inverter2211, and the inverter 2212 constitute a one-bit counter circuitchanging the level of the signal XADD12 from “H” to “L” or from “L” to“H” whenever the signal XADD11 (not shown) is changed from the “L” levelto the “H” level. Accordingly, a 13-bit counter circuit is constitutedby the circuits and the signal XADD0, the signal XADD1, . . . , and thesignal XADD12 are output as the count result of the 13-bit counter. Thatis, the signal XADD0, the signal XADD1, and the signal XADD12 form a13-bit signal counted up to “0”, “1”, “2”, “3”, . . . , “2¹³−2(=8192−2)”, “2¹³−1 (=8192−1)”, “0”, “1”, “2”, “3”, . . . whenever theinverted signal of the highest bit signal RBA1 as the carry signal ofthe bank address counter 21 is changed from the “H” level to the “L”level.

The configuration and the operation of the refresh start signalgenerator circuit 10 shown in FIG. 1 will be described with reference toFIGS. 8 and 9. FIG. 8 is a block diagram illustrating the configurationof the refresh start signal generator circuit 10 shown in FIG. 1. FIG. 9is a timing diagram illustrating operating waveforms of the units of thesemiconductor memory device 1 shown in FIG. 1. Here, in FIG. 9, the4KREF mode in which the refresh process is performed twice during thetRFC period, the 5.3KREF mode in which 1.5 refresh processes areperformed during the same period, and the 8KREF mode in which onerefresh process is performed during the same period are verticallyarranged in this order. In this case, signal waveforms of the refreshsignal MCRFT, the refresh start signal RREFT, the bank address BADD, andthe refresh control signals PMCBATi (where i is an integer of 0 to 7)are shown every mode. The count value of the bank address BADD isexpressed by numerals (“0” to “3”), the signal generation time of therefresh control signals PMCBATi (where i is an integer of 0 to 7) isexpressed by waveforms, and the values of the X addresses XADD suppliedfrom the X address selector/buffer circuit 60 to the memory banks areexpressed by numerals surrounded with parentheses (“(0000)”, “(0001)”, .. . ).

The refresh start signal generator circuit 10 shown in FIG. 8 includesthree blocks 11, 12, and 13, and a two-AND-OR complex gate 14. The block11 is a circuit outputting four pulse-like signals in response to therefresh signal MCRFT input from the command receiver/decoder 40 shown inFIG. 1. The complex gate 14 outputs four pulse-like refresh startsignals RREFT on the basis of the output of the block 11 (for example,four pulse-like refresh start signals RREFT generated at times t1, t2,t3, and t4 in FIG. 9).

In the example shown in FIG. 8, the block 11 includes three delayelements 1101, 1102, and 1103 connected in series to each other, aninverter 1105 having the refresh signal MCRFT as an input, threeinverters 1106, 1107, and 1104 having the outputs of the delay elements1101, 1102, and 1103 as their inputs, respectively, and a NAND gate 1108having the outputs of the inverters 1105, 1106, 1107, and 1104 as fourinputs. The refresh signal MCRFT is input to the delay element 1101. Theoutput of the NAND gate 1108 is connected to the OR input of the complexgate 14.

The block 12 outputs a pulse-like signal at different falling times ofthe refresh control signals PMCBATi input from the refresh operationcontrol circuit 50 shown in FIG. 1. In this embodiment, the refreshcontrol signals PMCBAT0 and PMCBAT7, the refresh control signals PMCBAT4and PMCBAT3, the refresh control signals PMCBAT1 and PMCBAT6, and therefresh control signals PMCBAT5 and PMCBAT2 are signals having the sametiming. Accordingly, when each refresh control signal PMCBATi falls once(is changed from “H” to “L”), four pulse-like signals in total areoutput. Since the output of the block 12 is connected to the AND inputof the complex gate 14, the pulse-like signal can be generated as theoutput of the complex gate 14 or not depending on the output signal ofthe block 13 which is another AND input. In the example shown in FIG. 9,four pulse-like refresh start signals RREFT are output at times t5, t6,t7, and t8 in the 4KREF mode depending on the output of the block 12.Two pulse-like refresh start signals RREFT are output at times t5 and t6in the 5.3KREF mode depending on the output of the block 12. However,the refresh start signal RREFT is not generated in the 8KREF modedepending on the output of the block 12.

In the example shown in FIG. 8, one pulse-like signal is generated incorrespondence to the falling of the refresh control signals PMCBAT0 andPMCBAT7 by a NOR gate 1201 having the refresh control signals PMCBAT0and PMCBAT7 as two inputs, a delay element 1202 having the output of theNOR gate 1201 as an input, and a NAND gate 1203 having the output of theNOR gate 1201 as a positive logical input and the output of the delayelement 1202 as a negative logical input. One pulse-like signal isgenerated in correspondence to the falling of the refresh controlsignals PMCBAT4 and PMCBAT3 by a NOR gate 1204 having the refreshcontrol signals PMCBAT4 and PMCBAT3 as two inputs, a delay element 1205having the output of the NOR gate 1204 as an input, and a NAND gate 1206having the output of the NOR gate 1204 as a positive logical input andthe output of the delay element 1205 as a negative logical input. Onepulse-like signal is generated in correspondence to the falling of therefresh control signals PMCBAT1 and PMCBAT6 by a NOR gate 1207 havingthe refresh control signals PMCBAT1 and PMCBAT6 as two inputs, a delayelement 1208 having the output of the NOR gate 1207 as an input, and aNAND gate 1209 having the output of the NOR gate 1207 as a positivelogical input and the output of the delay element 1208 as a negativelogical input. One pulse-like signal is generated in correspondence tothe falling of the refresh control signals PMCBAT2 and PMCBAT5 by a NORgate 1210 having the refresh control signals PMCBAT2 and PMCBAT5 as twoinputs, a delay element 1211 having the output of the NOR gate 1210 asan input, and a NAND gate 1212 having the output of the NOR gate 1210 asa positive logical input and the output of the delay element 1211 as anegative logical input. The output of a NAND gate 1213 having theoutputs of the NANDs 1203, 1206, 1209, and 1212 as four inputs isconnected to the AND input of the complex gate 14.

The block 13 constitutes a counter counting the number of pulse-likeactivating signals RREFT output from the complex gate 14 while changingthe maximum value of the count value depending on the refresh modes. Theblock 13 outputs a signal in the “H” level before the counter of theblock 13 reaches the maximum value, and outputs a signal in the “L”level when the counter of the block 13 reaches the maximum value. Theoutput of the block 13 is input to the AND input of the complex gate 14of which one AND input is connected to the output of the block 12.Accordingly, after the output of the block 13 reaches the “L” level, thepulse-like refresh start signal RREFT corresponding to the output of theblock 12 is not output from the complex gate 14. That is, after thenumber of pulse-like signals of the input refresh start signals RREFTreaches the maximum value set depending on the refresh modes, therefresh start signal RREFT based on the output of the block 12 is notgenerated.

Specifically, when 8 refresh start signals RREFT are generated in the4KREF mode, the output of the block 13, that is, the output of theinverter 1317, is changed to the “L” level. When 6 refresh start signalsRREFT are generated in the 5.3KREF mode, the output of the block 13,that is, the output of the inverter 1317, is changed to the “L” level.When 4 refresh start signals RREFT are generated in the 8KREF mode, theoutput of the block 13, that is, the output of the inverter 1317, ischanged to the “L” level. The counter of the block 13 is reset by theinput of the next refresh start signal RREFT after reaching the maximumvalue, and counts up to “0”, “1”, . . . , again. After the maximum valueis reached (after the output of the block 13 is changed to the “L”level), the refresh start signal RREFT is not generated in accordancewith the output of the block 12. Accordingly, only when the refreshstart signal RREFT is generated in accordance with the output of theblock 11, that is, the refresh signal MCRFT, the counter of the block 13is reset and counts up again. In the example shown in FIG. 9, thenumbers of output refresh start signals RREFT in the refresh modes aredifferent from each other depending on the output of the block 12, thatis, depending on the falling of the refresh control signal PMCBATi,which is because the maximum value set in the counter of the block 13 ischanged.

In the example shown in FIG. 8, in the block 13, a lowest-bit counter isconstituted by a D flip-flop 1301, a D flip-flop 1302, an inverter 1303,and an inverter 1304. In this case, the output Q of the D flip-flop 1301is connected to the input D of the D flip-flop 1302, the output Q of theD flip-flop 1302 is connected to the input of the inverter 1303, and theoutput of the inverter 1303 is connected to the input D of the Dflip-flop 1301. The refresh start signal RREFT output from the complexgate 14 is input to the clock input CK of the D flip-flop 1301 and theinverter 1304, and the output of the inverter 1304 is input to the clockinput CK of the D flip-flop 1302. The output of the NAND gate 1316 isconnected to the reset input of the D flip-flop 1301.

In the block 13, a second-bit counter is constituted by a D flip-flop1305, a D flip-flop 1306, an inverter 1307, and an inverter 1308. Inthis case, the output Q of the D flip-flop 1305 is connected to theinput D of the D flip-flop 1306, the output Q of the D flip-flop 1306 isconnected to the input of the inverter 1307, and the output of theinverter 1307 is connected to the input D of the D flip-flop 1305. Theoutput of the inverter 1303 in the first-bit counter is input to theclock input CK of the D flip-flop 1305 and the inverter 1308, and theoutput of the inverter 1308 is input to the clock input CK of the Dflip-flop 1306. The output of the NAND gate 1316 is connected to thereset input of the D flip-flop 1305.

In the block 13, a third-bit counter is constituted by a D flip-flop1309, a D flip-flop 1310, an inverter 1311, and an inverter 1312. Inthis case, the output Q of the D flip-flop 1309 is connected to theinput D of the D flip-flop 1310, the output Q of the D flip-flop 1310 isconnected to the input of the inverter 1311, and the output of theinverter 1311 is connected to the input D of the D flip-flop 1309. Theoutput of the inverter 1307 in the second-bit counter is input to theclock input CK of the D flip-flop 1309 and the inverter 1312, and theoutput of the inverter 1312 is input to the clock input CK of the Dflip-flop 1310. The output of the NAND gate 1316 is connected to thereset input of the D flip-flop 1309.

The block 13 includes NAND gates 1313, 1314, 1315, and 1316 as a circuitfor setting the maximum value of the three-bit counter. The M4KREFTsignal output from the refresh number setting circuit 80 and the outputsof the D flip-flops 1302, 1306, and 1310 are input to the NAND 1313.Accordingly, the output of the NAND gate 1313 is in the “L” level whenthe M4KREFT signal is in the “H” level and the outputs of the three-bitcounter are all in the “H” level (=“111”=7). The M53KREFT signal outputfrom the refresh number setting circuit 80 and the outputs of the Dflip-flop 1302, the inverter 1307, and the D flip-flop 1310 are input tothe NAND 1314. Accordingly, the output of the NAND gate 1314 is in the“L” level when the M53KREFT signal is in the “H” level and the outputsof the three-bit counter are “101”=5. The M8KREFT signal output from therefresh number setting circuit 80 and the outputs of the D flip-flops1302 and 1306 and the inverter 1311 are input to the NAND 1315.Accordingly, the output of the NAND gate 1315 is in the “L” level whenthe M8KREFT signal is in the “H” level and the outputs of the three-bitcounter are “011”=3.

The NAND 1316 outputs the signal in the “H” level when one output of theNAND gates 1313, 1314, and 1315 is in the “L” level, that is, when thecount value reaches the maximum value in any refresh mode. The inverter1317 inverts the output of the NAND gate 1316. Accordingly, the outputof the inverter 1317 is in the “L” level when the count value reachesthe maximum value in any refresh mode, and is in the “H” level beforethe count value reaches the maximum value. When the output of the NANDgate 1316 is changed to the “H” level, the D flip-flops 1301, 1305, and1309 are reset and the outputs Q of the D flip-flops 1301, 1305, and1309 are changed to the “L” level. However, the outputs Q of the Dflip-flops 1302, 1306, and 1310 are retained in the maximum value whenthe D flip-flops 1301, 1305, and 1309 are reset, and the outputs Q arereset to the “L” level when the clock input CK of the D flip-flops 1302,1306, and 1310 are changed to the “H” level.

According to the above-mentioned configuration, as shown in FIG. 9, whenthe refresh signal MCRFT is generated in the 4KREF mode (time t1), therefresh start signal RREFT is output four times from the refresh startsignal generator circuit 10 (times t1, t2, t3, and t4). The countercircuit 20 counts up the bank address BADD from “0” to “1”, “2”, “3”,and “0” in response to the four refresh start signals RREFT, when theinitial values before time t1 are all “0”. When the bank address BADDcarries (returning to “0” at “3”) in response to the refresh startsignal RREFT at time t4, the X address XADD is changed to “0001” fromthe initial value “0000”. Here, the X address selector/buffer circuit 60receives, retains, and outputs the X address XADD at times t1, t2, t3,and t4 when the refresh start signals RREFT are generated, respectively.Accordingly, until the next refresh start signal RREFT is generated attime t5, the X address XADD of the refresh target is not changed fromthe initial value “0000”.

As shown in FIG. 9, the refresh control signals PMCBATi are changed tothe “H” level by the refresh operation control circuit 50 on the basisof the refresh start signals RREFT and the bank address BADD. Therefresh operation control circuit 50 sets the refresh control signalsPMCBATi to the “H” level for a predetermined time necessary for therefresh process and then sets the refresh control signals PMCBATi to the“L” level. With the falling from the “H” level to the “L” level, therefresh start signal RREFT is output four times from the refresh startsignal generator circuit 10 (at times t5, t6, t7, and t8, respectively).

The counter circuit 20 counts up the bank address BADD from “0” to “1”,“2”, “3”, and “0” in response to the four refresh start signals RREFT atthe second time. When the bank address BADD carries (returning to “0” at“3”) in response to the refresh start signal RREFT at time t8, the Xaddress XADD is changed to “0002” from the initial value “0001”. Here,the X address selector/buffer circuit 60 receives, retains, and outputsthe X address XADD at times t5, t6, t7, and t8 when the refresh startsignals RREFT are generated, respectively. Accordingly, until the nextrefresh start signal RREFT is generated at time t9, the X address XADDof the refresh target is not changed from the value “0001”.

As shown in FIG. 9, the refresh control signals PMCBATi are changed tothe “H” level by the refresh operation control circuit 50 on the basisof the refresh start signals RREFT and the bank address BADD. Therefresh operation control circuit 50 sets the refresh control signalsPMCBATi to the “H” level for a predetermined time necessary for therefresh process and then sets the refresh control signals PMCBATi to the“L” level. At time t8, the number of generated refresh start signalsRREFT in the 4KREF mode reaches 8 which is the maximum value.Accordingly, after time t8, the refresh start signal RREFT is notgenerated with the falling of the refresh control signals PMCBATi.

When the auto-refresh command is input and the refresh signal MCRFT isgenerated (time t9), 8 (=4+4) refresh start signals RREFT are generatedagain (times t9, t10, t11, t12, t13, t14, t15, and t16), and the bankaddress BADD is changed from “0” to “1”, “2”, “3”, “0”, “1”, “2”, “3”,and “0”. Since the bank address BADD is changed from “3” to “0” twice,the X address is changed from “0002” to “0003” and from “0003” to“0004”. Here, at times t9 to t12, the X address XADD input to the Xaddress selector/buffer circuit 60 is retained in “0002”. At times t13to t16, the X address XADD input to the X address selector/buffercircuit 60 is retained in “0003”.

In this way, when two auto-refresh commands are input in the 4KREF mode,the refresh process for the X addresses of “0000” to “0003” is performedon all the memory banks 0 (100) to 7 (170).

In the 5.3KREF mode, when the refresh signal MCRFT is generated (timet1), the refresh start signal RREFT is output four times from therefresh start signal generator circuit 10 (times t1, t2, t3, and t4).The counter circuit 20 counts up the bank address BADD from “0” to “1”,“2”, “3”, and “0” in response to the four refresh start signals RREFT,when the initial values before time t1 are all “0”. When the bankaddress BADD carries (returning to “0” at “3”) in response to therefresh start signal RREFT at time t4, the X address XADD is changed to“0001” from the initial value “0000”. Here, the X addressselector/buffer circuit 60 receives, retains, and outputs the X addressXADD at times t1, t2, t3, and t4 when the refresh start signals RREFTare generated, respectively. Accordingly, until the next refresh startsignal RREFT is generated at time t5, the X address XADD of the refreshtarget is not changed from the initial value “0000”.

As shown in FIG. 9, the refresh control signals PMCBATi are changed tothe “H” level by the refresh operation control circuit 50 on the basisof the refresh start signals RREFT and the bank address BADD. Therefresh operation control circuit 50 sets the refresh control signalsPMCBATi to the “H” level for a predetermined time necessary for therefresh process and then sets the refresh control signals PMCBATi to the“L” level. With the falling of the refresh control signals PMCBAT<0/7>and PMCBAT<4/3> from the “H” level to the “L” level, the refresh startsignal RREFT is output twice from the refresh start signal generatorcircuit 10 (at times t5 and t6, respectively). At time t6, the number ofgenerated refresh start signals RREFT in the 5.3KREF mode reaches 6which is the maximum value. Accordingly, after time t8, the refreshstart signal RREFT is not generated with the falling of the refreshcontrol signals PMCBAT<1/6> and PMCBAT<5/2>.

The counter circuit 20 counts up the bank address BADD from “0” to “1”and “2” in response to the two refresh start signals RREFT at the secondtime. The X address selector/buffer circuit 60 receives, retains, andoutputs the X address XADD at times t5 and t6 when the refresh startsignals RREFT are generated; respectively. Accordingly, until the nextrefresh start signal RREFT is generated at time t9, the X address XADDof the refresh target is retained in the value “0001”.

As shown in FIG. 9, two sets of refresh control signals PMCBAT<0/7> andPMCBAT<4/3> are changed to the “H” level (times t5 and t6) by therefresh operation control circuit 50 on the basis of the refresh startsignals RREFT and the bank address BADD. The refresh operation controlcircuit 50 sets the refresh control signals PMCBAT<0/7> and PMCBAT<4/3>to the “H” level for a predetermined time necessary for the refreshprocess and then sets the refresh control signals PMCBAT<0/7> andPMCBAT<4/3> to the “L” level.

When the refresh signal MCRFT is generated (time t9), 6 (=4+2) refreshstart signals RREFT are generated again (times t9, t10, t11, t12, t13,and t14), and the bank address BADD is changed from “2” to “3”, “0”,“1”, “2”, “3”, and “0”. Since the bank address BADD is changed from “3”to “0” twice, the X address is changed from “0001” to “0002” and from“0002” to “0003”. Here, at times t9 and t10, the X address XADD input tothe X address selector/buffer circuit 60 is retained in “0001”. At timest11 to t14, the X address XADD input to the X address selector/buffercircuit 60 is retained in “0002”.

In this way, when two auto-refresh commands are input in the 5.3KREFmode, the refresh process for the X addresses of “0000” to “0002” isperformed on all the memory banks 0 (100) to 7 (170).

In the 8KREF mode, when the refresh signal MCRFT is generated (time t1),the refresh start signal RREFT is output four times from the refreshstart signal generator circuit 10 (times t1, t2, t3, and t4). Thecounter circuit 20 counts up the bank address BADD from “0” to “1”, “2”,“3”, and “0” in response to the four refresh start signals RREFT, whenthe initial values before time t1 are all “0”. When the bank addressBADD carries (returning to “0” at “3”), the X address XADD is changed to“0001” from the initial value “0000”. Here, the X addressselector/buffer circuit 60 receives, retains, and outputs the X addressXADD at times t1, t2, t3, and t4 when the refresh start signals RREFTare generated, respectively. Accordingly, until the next refresh startsignal RREFT is generated at time t5, the X address XADD of the refreshtarget is not changed from the initial value “0000”.

As shown in FIG. 9, the refresh control signals PMCBATi are changed tothe “H” level by the refresh operation control circuit 50 on the basisof the refresh start signals RREFT and the bank address BADD (times t1,t2, t3, and t4). The refresh operation control circuit 50 sets therefresh control signals PMCBATi to the “H” level for a predeterminedtime necessary for the refresh process and then sets the refresh controlsignals PMCBATi to the “L” level. At the time point when the fourthrefresh start signal RREFT is generated at time t4, the number ofgenerated refresh start signals RREFT in the 8KREF mode reaches 4 whichis the maximum value. Accordingly, in the 8KREF mode, the refresh startsignal RREFT is not generated with the falling of the refresh controlsignals PMCBATi.

When the refresh signal MCRFT is generated (time t9), 4 refresh startsignals RREFT are generated again (times t9, t10, t11, and t12), and thebank address BADD is changed from “0” to “1”, “2”, “3”, and “0”. Sincethe bank address BADD is changed from “3” to “0” once, the X address ischanged from “0001” to “0002”. Here, at times t9, t10, t11, and t12, theX address XADD input to the X address selector/buffer circuit 60 isretained in “0001”.

In this way, when the auto-refresh command is input twice in the 8KREFmode, the refresh process for the X addresses of “0000” to “0001” isperformed on all the memory banks 0 (100) to 7 (170).

As described above, in this embodiment, when the auto-refresh command isdecoded and the refresh signal MCRFT is changed to the “H” level, theinformation of the outputs THTEMPT and TLTEMPT of the temperaturedetector circuit 70 is latched by the D latch of the refresh numbersetting circuit 80. The refresh controller 2 operates on the basis ofthe latched outputs THTEMPT and TLTEMPT, and the refresh operation isperformed on the memory banks 0 (100) to 7 (170). When the refreshsignal MCRFT is changed from “L” to “H” after the refresh operation isended, the outputs THTEMPT and TLTEMPT of the temperature detectorcircuit 70 are input to the D latch of the refresh number settingcircuit 80.

Although it has been described in this embodiment that the refreshoperation is performed in a time division manner by two banks, themethod of performing a refresh operation may be modified in variousforms such as a method of refreshing all the banks at a time or a methodof refreshing the banks in a time division manner four banks at a time.The method of counting the X address XADD is not particularly limited.

Another embodiment of the invention will be described now with referenceto FIG. 10. In a semiconductor memory device 1 a shown in FIG. 10, atemperature detector circuit 70 a, a refresh number setting circuit 80a, and a refresh controller 2 a are provided instead of the temperaturedetector circuit 70, the refresh number setting circuit 80, and therefresh controller 2 shown in FIG. 1. The temperature detector circuit70 a is obtained by removing the circuit (such as the comparator 712)used for the output of the signal TLTEMPT from the temperature detectorcircuit 70 shown in FIG. 2. The refresh number setting circuit 80 aincludes a D flip-flop 830 latching the signal THTEMPT output from thetemperature detector circuit 70 a in response to the refresh signalMCRFT (using the refresh signal MCRFT as the clock input CK) and a Dflip-flop 831 latching the signal obtained by inverting the signalTHTEMPT by the use of the inverter 832. The output of the D flip-flop830 is input as the M4KREF signal to the refresh controller 2 a and theoutput of the D flip-flop 831 is input as the M8KREF signal to therefresh controller 2 a. The refresh controller 2 a has almost the sameconfiguration as the above-mentioned embodiment, that is, aconfiguration in which a circuit for fixing the M53KREF signal to the“L” level is added thereto.

In this embodiment, the refresh modes are limited to two of the 4KREFmode and the 8KREF mode. The temperature detector circuit 70 a operatesso as to set the signal THTEMPT to the “L” level when the temperature isequal to or lower than a predetermined temperature and to set the signalTHTEMPT to the “H” level when the temperature is higher than thepredetermined temperature. The operation mode can be switched betweentwo modes of the 8KREF mode at a low temperature and the 4KREF mode at ahigh temperature. The operation mode is switched between 8K and 4K inFIG. 10, but combinations of 8K and 5.3K or 5.3K and 4K may beconsidered. A method of 16KREF mode (16K-refresh) may be employed inpowerful products.

For the semiconductor memory device 1 in accordance with thisembodiment, the configurations and operations to control theauto-refresh have been descried above. The semiconductor memory device 1in accordance with this embodiment may be configured to select one ofthe auto-refresh and self-refresh operations to perform the refreshoperation of the memory cells. The known configurations and operationsfor controlling the self-refresh may be available. An example of theconfiguration to perform the self-refresh operation will be describedwith reference to FIGS. 11 and 12.

FIG. 11 is a block diagram illustrating a semiconductor memory deviceincluding an oscillator 90 which controls self-refresh operations. Thesemiconductor memory device 1 shown in FIG. 11 is different from thesemiconductor device 1 shown in FIG. 1 in further including theoscillator 90. The command receiver/decoder 40 generates the refreshexecution signal MCRFT and activates a self-refresh state signal SELFwhen the decoded command CMD is the self-refresh command. Theself-refresh state signal SELF is maintained active, for example, in the“H” level in a period of time when the self-refresh operation isperformed. Once the oscillator 90 receives the activated self-refreshstate signal SELF, the oscillator 90 supplies an internal refreshcommand IREF to the command receiver/decoder 40 at a predeterminedcycle. The command receiver/decoder 40 activates the refresh executionsignal MCRFT every time the command receiver/decoder 40 receives theinternal refresh command IREF. The oscillator 90 changes the cycle, atwhich the external refresh command IREF is output, based on the signalsTHTEMPT and TLTEMPT which has been output from the temperature detectorcircuit 70. The self-refresh state signal SELF which has been outputfrom the command receiver/decoder 40 is also supplied to the refreshnumber setting circuit 80.

FIG. 12 is a circuit diagram illustrating the configuration of therefresh number setting circuit included in the semiconductor device ofFIG. 11. The refresh number setting circuit 80 of FIG. 12 is differentfrom the refresh number setting circuit 80 of FIG. 5 in having logiccircuits 821, 822 and 823. In FIG. 12, when the self-refresh statesignal SELF is active and in the “H” level, the signals M53KREFT andM4KREFT are in the “L” level. The semiconductor device 1 of FIGS. 11 and12 is configured to perform the self-refresh operations in the M8KREFTmethod. When the self-refresh state signal SELF is inactive and in the“L” level, logic levels of the output signals from the logic circuits821, 822 and 823 are the same as the logic levels of the output signalsfrom the corresponding logic circuits 803, 804 and 805, respectively.Namely, when the self-refresh state signal SELF is inactive and in the“L” level, the above-described auto-refresh operation is performed.

FIG. 12 illustrates the refresh operations in accordance with theM8KREFT method. The method of the refresh operations should not belimited to this M8KREFT method. Other methods such as the M4KREFT andM53KREFT methods may be available to perform the refresh operations,even it is necessary to modify the configurations of the logic circuits821, 822, and 823.

When executing the auto-refresh operation, the semiconductor memorydevice 1 adjusts or changes the number of refresh operations executed inresponse to a single auto-refresh command which is input from outside,in order to reduce the current consumption. The adjustment or change inthe number of refresh operations is made based depending upon atemperature variation of the semiconductor device 1.

When executing the self-refresh operation, the semiconductor memorydevice 1 adjusts or change an adjustable cycle time, based on thetemperature variation of the semiconductor device 1, to reduce thecurrent consumption. An internal refresh command is generated inresponse to an external refresh-command at the adjustable cycle time.The semiconductor memory device 1 fixes the number of self-refreshoperations to be executed in response to a single internal refreshcommand. The number of self-refresh operations to be executed inresponse to a single internal refresh command is fixed independent fromthe temperature variation of the semiconductor device 1.

As described above, the semiconductor memory device according to theinvention is a semiconductor memory device in which a memory devicedivided into plural memory banks is disposed in a part of thesemiconductor device and which selects one of the auto-refresh mode andthe self refresh mode to refresh the memory device. Here, the number ofrefresh processes to be performed is selected depending on thetemperature of the semiconductor device whenever a command for selectingthe auto-refresh mode is detected. According to this configuration, byswitching the operation mode of the auto-refresh operation depending onthe temperature, it is possible to reduce the number of operations inthe tRFC at a low temperature, thereby reducing the current consumption.At a high temperature, it is possible to enhance the number ofoperations in the tRFC, thereby preventing the loss of data. As aresult, it is possible to optimize the auto-refresh operation dependingon the operation state of the system.

The semiconductor memory device according to the invention includes thetemperature detector circuit being formed in a part of the semiconductordevice and detecting the temperature of the semiconductor device, thecommand receiver/decoder receiving and decoding an external command andoutputting the refresh signal MCRFT when the decoding result is theauto-refresh command, the refresh start signal generator circuitoutputting the refresh start signal RREFT by a predetermined number oftimes on the basis of the temperature detection result in response tothe refresh signal MCRFT, the bank address counter counting the bankaddress for selecting a specific memory bank out of the plural memorybanks using the number of times determined depending on the temperatureas a limit in response to the refresh signal and carrying at thedivision number of refresh operations on the memory banks, and the Xaddress counter counting up the X address for selecting a word line inthe memory bank with the carry. According to this configuration, thenumber of refresh operations can be selected on the basis of thetemperature detection result whenever the auto-refresh command is input.Accordingly, it is possible to optimize the operation state with a goodresponse to the variation in temperature.

Since the temperature detector circuit detects the temperature usingplural power source circuits having different temperaturecharacteristics and formed in a part of the semiconductor device, it ispossible to smoothly manage the characteristics or the precision of thecircuit elements, compared with the case where a circuit detecting thetemperature using a single power source circuit is provided.

Since the refresh number setting circuit outputting the signalindicating the number of output refresh start signals RREFT to therefresh start signal generator circuit while retaining the output stateevery input of the refresh signal MCRFT on the basis of the output ofthe temperature detector circuit is provided, it is possible tostabilize the signal indicating the number of output refresh startsignals RREFT and thus to easily prevent unstable operation at the timeof switching the refresh operation.

Since the refresh control circuit controlling the refresh operation onthe memory bank selected by the bank address input from the bank addresscounter in response to the input of the refresh start signal RREFT andthe X address selector/buffer circuit selecting the X address input fromthe X address counter and outputting the selected X address to theplural memory banks in response to the input of the refresh start signalRREFT are provided, it is possible to easily and stably perform thecounting operation of the X address even at the time of switching therefresh operation.

The semiconductor memory device in the claims corresponds to thesemiconductor memory device 1 or 1 a. The temperature detector in theclaims corresponds to the temperature detector circuit 70. The commanddecoder in the claims corresponds to the command receiver/decoder 40.The refresh start signal generator circuit in the claims corresponds tothe refresh start signal generator circuit 10. The bank address counterin the claims corresponds to the bank address counter 21. The X addresscounter in the claims corresponds to the X address counter 22. Therefresh number setting unit in the claims corresponds to the refreshnumber setting circuit 80. The refresh controller in the claimscorresponds to the refresh operation control circuit 50. The X addressselector in the claims corresponds to the X address selector/buffercircuit 60.

The term “configured” is used to describe a component, section or partof a device includes hardware and/or software that is constructed and/orprogrammed to carry out the desired function.

It is apparent that the present invention is not limited to the aboveembodiments, but may be modified and changed without departing from thescope and spirit of the invention.

1. A semiconductor device comprising: an auto-refresh command detectorthat detects an auto-refresh command; and a refresh number setting unitthat sets the number of auto-refresh to be performed in a period oftime, based on temperature, when the auto-refresh command detectordetects the auto-refresh command.
 2. The semiconductor device accordingto claim 1, further comprising: a temperature detector that detects atemperature of the semiconductor device, wherein the refresh numbersetting unit sets the number of refresh based on the temperaturedetected by the temperature detector.
 3. The semiconductor deviceaccording to claim 1, further comprising: a command decoder that decodesan external command, the command decoder outputting a refresh executionsignal if the decoded command is to select auto-refresh; and a refreshstart signal generator that outputs a predetermined number of refreshstart signal based on the refresh execution signal and the detectedtemperature.
 4. The semiconductor device according to claim 3, furthercomprising: a plurality of memory banks; a temperature detector thatdetects a temperature of the semiconductor device; and a bank addresscounter that counts a bank address up to an upper limit based on therefresh execution signal, the upper limit being determined based on thedetected temperature, the bank address specifying a memory bank in theplurality of memory banks, the bank address counter carrying a countingnumber at a division number, the division number being the number oftime-division by which refresh is performed to the plurality of memorybanks.
 5. The semiconductor device according to claim 4, furthercomprising: an address counter that counts up an address when carryingthe counting number, the address selecting a word line of the pluralityof memory banks.
 6. The semiconductor device according to claim 4,wherein the temperature detector detects the temperature by using aplurality of power units having different temperature characteristics.7. The semiconductor device according to claim 4, wherein the refreshnumber setting unit supplies a signal to the refresh start signalgenerator, the signal designating the number of outputs of the refreshstart signal, the refresh number setting unit supplies the signal, basedon the temperature detected by the temperature detector, in response toeach occurrence of the refresh execution signal.
 8. The semiconductordevice according to claim 7, further comprising: a refresh controllerthat controls refresh operations of a selected memory bank of theplurality of memory banks, the selected memory bank being selected bythe bank address supplied from the bank address counter, the refreshcontroller controlling the refresh operations in response to an input ofthe refresh start signal; and an address selector that selects anaddress supplied from the address counter, in response to the input ofthe refresh start signal, the address selector supplying the address tothe plurality of bank addresses.
 9. A device comprising: a commanddecoder configured to generate a refresh execution signal in response toeach occurrence of an auto-refresh command; a refresh start signalgenerator configured to generate a refresh start signal a variablenumber of times in response to each occurrence of the refresh executionsignal; a refresh number setting unit configured to designate thevariable number in response to a temperature of the device; a memorycell array; and a refresh control circuit configured to perform arefresh operation on the memory cell array in response to eachoccurrence of the refresh start signal.
 10. The device according toclaim 9, further comprising a temperature detector configured to detectthe temperature of the device, wherein the refresh number setting unitis configured to change the variable number in response to a variationof the temperature of the device.
 11. The device according to claim 10,wherein the temperature detector includes a plurality of power unitsthat represent different temperature characteristics from each other.12. A device comprising: a command decoder configured to generate arefresh execution signal in response to each occurrence of anauto-refresh command; a refresh start signal generator configured togenerate a first number of refresh start signals in response to eachoccurrence of the refresh execution signal when the device is at a firsttemperature and generate in succession a second number of the refreshstart signals in response to each occurrence of the refresh executionsignal when the device is at a second temperature different from thefirst temperature, the first number of the refresh start signals beingdifferent from the second number of the refresh start signals; a memorycell array; and a refresh control circuit configured to perform arefresh operation on the memory cell array in response to eachoccurrence of the refresh start signals.
 13. The device as claimed inclaim 12, wherein an interval between one of the first number of refreshstart signals and another one of the first number of refresh startsignals that succeeds the one of the first number of refresh startsignals is substantially equal to an interval between one of the secondnumber of refresh start signals and another one of the second number ofrefresh start signals that succeeds the one of the second number ofrefresh start signals.
 14. The device as claimed in claim 12, furthercomprising a refresh number setting unit configured to supply, in afirst condition, the refresh start signal generator with a first signalthat designates generation of the first number of refresh start signalsand to supply, in a second condition, the refresh start signal generatorwith a second signal that designates generation of the second number ofrefresh start signals.
 15. The device as claimed in claim 14, furthercomprising a temperature detection circuit detecting the temperature ofthe device and supplying a result of the detection to the refresh numbersetting unit.
 16. The device according to claim 15, wherein thetemperature detector includes a plurality of power units that representdifferent temperature characteristics from each other.
 17. The device asclaimed in claim 12, wherein the first temperature is greater than thesecond temperature and the first number is greater than the secondnumber.
 18. The device as claimed in claim 12, wherein the commanddecoder is configured to activate a self-refresh state signal inresponse to each occurrence of a self-refresh command, and the devicefurther comprises an oscillation circuit activated in response to theactivation of the self-refresh state signal and producing, whenactivated, cyclically an internal refresh command, and wherein thecommand decoder is configured to generate the refresh execution signalin response to each occurrence of the internal refresh command and therefresh start signal generator is configured to generate in succession athird number of refresh start signals in response to each occurrence ofthe refresh execution signal in a third condition that the self-refreshstate signal is being activated.
 19. The device as claimed in claim 18,further comprising: a temperature detection circuit detecting atemperature of the device, and a cycle adjusting circuit changing acycle of generation of the internal refresh command by the oscillationcircuit in response to the temperature of the device.
 20. The device asclaimed in claim 18, wherein the first number is substantially equal tothe third number.